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Item specifics

Condition:
New: A brand-new, unused, unopened, undamaged item (including handmade items). See the seller's ...
Brand:
Bigjigs Rail
Colour:
Multicoloured
UPC:
691621090237











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How to interpret default setup and hold checks

In the post "setup and hold checks", we discussed the meaning and interpretation of setup and hold checks. We also discussed the terms "default setup check" and "non-default setup check" and same for hold checks. Essentially, every timing check, be it setup/hold check, data check or clock gating check follows a default edge-relationship depending upon the types of elements involved. For instance, default setup check or setup timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop is full cycle, whereas hold check path is zero cycle. Have you ever thought why is default behavior like this in case of setup and hold checks. Most of us find the setup and hold check interpretation confusing for many cases which are not straightforward, such as positive level-sensitive latch to positive level-sensitive latch timing path. And we believe what the STA tools show us in terms of setup and hold checks. In this post, we will discuss how we can demystify the edge-relationship for setup and hold checks.

For this, we need to understand state machine behavior. Each state of an FSM can be interpreted as an instant of time, and setup check is a bridge between two states of the FSM allowing smooth transition from one state to the next. Every opportunity to alter state machine can be interpreted as one state. For instance, for a state machine comprising only positive edge-triggered flip-flops, every positive edge of clock can be interpreted as a state. Similarly, for a state-machine comprising both positive edge-triggered and negative edge-triggered elements, each (positive or negative) edge is a state. Now, coming to level-sensitive elements, their capturing instant is spread over a time interval rather than being an edge. For example, a positive latch can capture data at any time between positive edge and negative edge. Thus, for a design comprising all kinds of level-sensitive and edge-sensitive elements, the states of the FSM mapped to time should look like as shown in figure 1.

Figure 1: State machine behavior of a generic design

The FSM behavior shown in figure 1 is in line with commonly understood default FSM behavior. The default setup and hold checks, which are a way of transitioning to adjacent next state, also function the same way. In other words, default behavior of simulation and timing tools is in line with figure 1. It is, of course, possible to design FSMs that do not follow figure 1 through introduction of multi-cycle paths, but if not specified manually, figure 1 is followed.

We will now discuss a rule that will help you to figure out default setup/hold checks between all sequential element types.

Rule for default setup check: The very next instant that the data can be captured right after it has been launched, forms the default setup check. For instance, consider a positive edge-triggered flip-flop launching data at T=10 ns, which is to be captured at another flip-flop with clock waveform as shown below (for both launch and capture elements). After T=10ns, the next instant that will capture the data at each type of flop and latch (either positive or negative) is given in figure 2.


Figure 2: Data capturing instances for different sequential element types

Thus, post 10 ns, a positive latch can capture at any instant of time between 10 ns and 15 ns, negative latch can capture the data at any instant between 15 ns and 20 ns; a positive flop will capture the data at 20 ns and a negative flop will capture data at 15 ns. These all form default setup check. The previous such instant that the data could have been captured forms the default hold check. For instance, for positive flop, the instant before 20 ns that could have captured the data is 10 ns itself. Similarly, for negative flop, hold check is at previous negative edge (10 ns launch -> 5ns capture). For positive latch, hold check is also the same as negative flop  (10 ns launch -> 5ns capture) and for negative latch, hold check is same as for positive flop (10 ns launch -> 10 ns capture).

In the below posts, we discuss default setup and hold checks for different elements and for different clock ratios. I hope it covers all. Please let me know for any feedback through comments or email (myblogvlsiuniverse@gmail.com).



Default Setup/hold checks - positive flop to negative flop timing paths

The launch/capture event of a positive edge-triggered flip-flop happens on every positive edge of the clock, whereas that of a negative edge-triggered flip-flop occurs on the negative edge of the flip-flop. In this post, we will discuss the default setup/hold checks different cases - same clock, 1:n clock ratio clock and n:1 ratio clock. And this should cover all the possible cases of setup/hold checks.

Case 1: Both flip-flops getting same clock

Figure 1: Pos-flop to neg-flop default setup/hold checks when clocks are equal in frequency

Figure 1 shows a timing path from a positive edge-triggered flip-flop to a negative edge-triggered flip-flop. Let us say the data is launched at instant of time "T", which is a positive edge. Then, the next negative edge following time "T" serves as the edge which captures this data; thus forming the default setup check. And the very previous negative edge serves as the hold check. This is shown in the first part of figure 1. Thus, in this case, both setup and hold checks are half cycle.

Setup and hold slack equations

Setup slack = Period(clk) + Tskew - Tclk_q - Tcomb - Tsetup

Hold slack = Tclk_q + Tcomb - Tskew - Thold


Case 2: Flip-flops getting clocks with frequency ratio N:1 and positive edge of launch clock coincides with negative edge of capture clock

One of the cases where this happens is when clock is divided by an even number. Another is when odd division is followed by inversion. The resulting waveform will be as shown in figure 2. In this case, each positive edge of launch flip-flop is capable of launching a fresh data, but will be overwritten by next data. Only the one which is launched on the positive edge closest to the negative edge of capture clock will get captured at the endpoint. Similarly, the data which is launched at the edge coinciding negative edge of capture clock must not overwrite the data captured at the same edge. The setup and hold checks, thus formed, are as shown in figure 2 below. The setup check is full cycle of launch clock, whereas hold check is a zero cycle check.


Figure 2: Default setup/hold checks for case 2

Setup and hold slack equations

Setup slack = period(launch_clock) + Tskew - Tclk_q - Tcomb - Tsetup

 Hold slack = Tclk_q + Tcomb - Tskew - Thold

  

Case 3: Flip-flops gettings clocks with frequency ration N:1 and positive edge of launch clock coincides with positive edge of capture clock

One of the cases where this happens is when capture of the data happens on an odd divided clock. The resulting setup and hold checks are as shown in figure 3. Both setup and hold checks are half cycle of faster launch clock.

Figure 3: Default setup/hold checks for case 3
Setup and hold slack equations

Setup slack = period(launch_clock)/2 + Tskew - Tclk_q - Tcomb - Tsetup

 Hold slack =  period(launch_clock)/2 + Tclk_q + Tcomb - Tskew - Thold

Case 4: Flip-flops getting clocks with frequency 1:N and positive edge of launch clock coincides with negative edge of capture clock

One of the cases is when division is performed after inversion of the master clock and data is launched on the divided clock. Figure 4 shows the default setup/hold checks for this case. In this case, setup check is equal to full cycle of faster clock and hold check is a zero cycle check.

Figure 4: Default setup/hold checks for case 4
Setup and hold slack equations

Setup slack = period(capture_clock) + Tskew - Tclk_q - Tcomb - Tsetup

 Hold slack = Tclk_q + Tcomb - Tskew - Thold

Case 5: Flip-flops getting clocks with frequency 1:N and positve edge of launch clock coincides with positive edge of capture clock

This is a case of even division, or inversion, followed by odd division, followed by inversion. The setup and hold checks, both are equal to half cycle of faster clock.

Setup and hold slack equations

Setup slack = period(capture_clock)/2 + Tskew - Tclk_q - Tcomb - Tsetup

 Hold slack =  period(capture_clock)/2 + Tclk_q + Tcomb - Tskew - Thold

Can you think of any other scenario of setup/hold checks for this case? Please feel free to share your views.